APPLICOS PA72 Platform

Each daughter board is optimized for best signal performance. A PA72 daughter board typically has Differential In-/Outputs, Low THD, Low Noise and High Accuracy. The base board contains a 2-channel high-stability and low-jitter PLL clock generator, trigger circuitry, and of course the PXI-bus interface. A digital voltmeter is available for self-calibration purposes (supported by the driver), and can also be used for custom development boards.

The base board is available with PXI bus interface (PA72) and PXI-Express bus interface (PA72e). Both baseboards accept the same daughter boards. The J2 connector is a small version (XJ4) to ensure both versions are hybrid-slot compatible.

PA72 Base board

The PA72 base board contains a clock generator, trigger circuitry, a digital voltmeter and the PXI bus interface. In the block diagram below, the base board functions are yellow and the daughter board functions are green. The clock generator is a low jitter PLL clock that has less than 0.5ps jitter for low loop filter bandwidths. With higher loop filter bandwidths, frequency settling time can be less than 250ms.The main clock frequency ranges from 2kHz up to 945MHz with a resolution of less than 1 kHz. Each daughter board slot has its own clock divider.

Therefore the clock for each daughter board can be different while maintaining proper synchronization. The PLL clock generator features a high stability, low noise and low jitter 10MHz on-board reference clock with 1ppm frequency stability. In addition the PLL can be locked to the PXI backplane clock or to an external reference clock. The on-board clock source can also be bypassed by an external direct clock.

The trigger input supports edge and level triggering and positive and negative going trigger signals. The trigger source can be software, PXI Star trigger, PXI Trigger 0-6 (3-6 inverted), or external (front). Additionally, digitizer boards can be set to edge-trigger on the analog input signal.