Wafer probing is an essential step in the production process of semiconductor products. After the chip design engineer has completed the design of a new chip, the wafer fab starts manufacturing. The wafer fab process is a complex sequence of various process steps such as photo litho, etching, oxidation, deposition of layers, and so on. Each step in the process must be completely controlled to achieve full chip functionality. During the semiconductor manufacturing process, up to 150-200 production steps take place. Our aim throughout the entire process is wafer surface uniformity. Layer thickness determines component specifications. At this moment, structure dimensions used on the chips are increasingly smaller and 0.3 - 0.2 µm are very common in chip manufacturing today. On the other hand, we want to produce as many chips simultaneously as possible, and therefore wafer sizes increase. Although 8" wafers are already standard, new fabs are starting with 12" wafers. If you realize, that there are almost 3,243 million square µm on an 8" wafer, and every chip must be identical with the same specifications, you can see that this is impossible. A certain level of tolerance must be accepted. The only way to find out if a chip is functional and if it's parameters are within the tolerances is by an ELECTRICAL TEST. This test can only be performed when the wafer has finished the production process. If semiconductor component manufacturers achieve yields above 90%, it must be seen as an outstanding performance for the equipment manufacturer, material suppliers and the wafer fab personnel.
Analysis
The electrical test is necessary to locate the fail chips on the wafer. If the test results are correctly interpreted, it is extremely valuable feedback to the wafer-fab process. Composite maps, consecutive fail monitoring, and consecutive fail-bin monitoring provides this feedback information.
Time is Money
Time is money, so we better use it well. Even though wafer probing is an essential step in the semiconductor manufacturing process, it does not mean we should spend a lot of time testing the wafers. The correct way to save time during wafer probing is to use smart patterns to step from one chip to the other by making use of already known problem areas. In the beginning of wafer probing, fail chips were marked with an ink dot. During the chip-assembly process, this ink-dotted chip was recognized by the Die-bonder and the chip was skipped for further process. Time can be saved if we can tell the Die-bonder where the good chips are located. Inking can become obsolete, along with the recognition time on the die-bonder.
Wafer Integrity and First-Die Integrity
Throughout the wafer manufacturing process, wafer identification is used to keep track of the wafer and to build a full manufacture history. Different types of wafer identifications are used, such as, laser scribes just above the "flat" of the wafer, bar codes or dot coding. A problem arises because the identification is already on the bare wafer and will face all the process steps. Some of those process steps are harmless for readability, but other processes can cause serious problems. When the wafer is on the wafer prober, all production steps have been performed and the wafer identification can be partly covered by a metal layer for example. This can influence the readability of the identification. With the new generation of personal computers and their computing power, it is possible to use algorithms and camera-systems, which are capable of reading partly covered identifications. We have integrated one of these camera systems in our prober controller. We can assure that the test results at the end of the wafer probe step are listed in a wafer map with the correct wafer identification. This file can then be uploaded to the die-bonder and only the good chips will be selected. Inkless assembly is a fact.
Another very important / essential item is First-Die integrity. We want to know if the results in the map will correlate with the physical locations on the wafer. This is especially important when relatively small chips must be processed. Due to the way that some automatic wafer probers profile and align, the actual location and map location can be a row and/or column out of sequence. This is unacceptable in general and for inkless assembly in particular. A wafer map must always match the physical locations on the wafer.
We have found a way to guarantee "first-die integrity" and have implemented this in our product.
<Universal User Interface
There are over 20,000 wafer probers in use worldwide, some from the older generation and some just recently installed. Operators and test engineers must be trained on to use each individual prober. Every prober has a different method for generating setup files and responding to alarm messages. It would make life much easier if a certain standard was introduced. A wizard-guided routine, which is prober independent, can achieve this goal. Setup files to be used could be converted to all supported types.
A Windows NT based system with a user-friendly graphical user interface will make every prober easy to understand and operate. Most common probers on the market are or will be implemented. Real-time wafer mapping is a standard feature offered by this Prober controller.
Intelligent Prober Control
An intelligent prober controller can add special functionality to older probers that are not supported as a standard. Multiple level sample probing with an "if-then-else" structure, will give the user a wide range of achieving the quality levels. Speed incensement by performing; multiple die probing, is just another example. (16 sites on an Electroglas 2001 is implemented at one of our customers, together with offline inking in edge mode did reduce the process time per wafer with an unbelievable amount, compared to single site and traditional offline inking) Avoiding specific restricted areas on the wafer with the probe-cards can be achieved with the powerful control map editor.
Customization
Most wafer prober users have their own specific requirements with regards to file formats, lot start routines, probe card touch down counters, alarm levels, monitor requirements, automatic report generation, and so on. The open structure in the program makes it possible to react on customer wishes very quickly. Additional functionality can be added using DLL-hooks in the software.
Wafer probing has never been so easy.
SE-PROBE
If you require more information on this product or on the contents of this article, please contact Salland Engineering. info@salland.com, tel +31.38.454.7702